// Copyright (C) 1953-2020 NUDT
// Verilog module name - host_input_queue 
// Version: HIQ_V1.0
// Created:
//         by - fenglin 
//         at - 10.2020
////////////////////////////////////////////////////////////////////////////
// Description:
//         control bufid of pkt transmitted to host to input queue
//             - write bufid of ts packet to ram of TIM; 
//             - write bufid of not ts packet to queue.
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module host_input_queue
(
       i_clk,
       i_rst_n,
       
       iv_bufid_network,
       i_bufid_wr_network,
	   
	   iv_desp_host    ,
	   i_desp_wr_host  ,
	   o_desp_ack_host ,
       
       ov_fifo_wdata,
       o_fifo_wr
);
// I/O
// clk & rst
input                  i_clk;
input                  i_rst_n;  
//tsntag & bufid input from host_port
input          [8:0]   iv_bufid_network;
input                  i_bufid_wr_network;

input          [8:0]   iv_desp_host    ;
input                  i_desp_wr_host  ;
output reg             o_desp_ack_host ;
//tsntag & bufid output
output reg     [8:0]   ov_fifo_wdata;
output reg             o_fifo_wr;
//***************************************************
//          control bufid to input queue 
//***************************************************
always @(posedge i_clk or negedge i_rst_n) begin
    if(!i_rst_n) begin
        ov_fifo_wdata <= 9'b0;
        o_fifo_wr     <= 1'b0;  

        o_desp_ack_host <= 1'b0;		
    end
    else begin
        if(i_bufid_wr_network == 1'b1)begin
            ov_fifo_wdata <= iv_bufid_network;//bufid
            o_fifo_wr <= 1'b1;
			o_desp_ack_host <= 1'b0;
        end
		else if(i_desp_wr_host == 1'b1)begin
            ov_fifo_wdata <= iv_desp_host;//bufid
            o_fifo_wr <= i_desp_wr_host & o_desp_ack_host;
            o_desp_ack_host <= 1'b1;			
		end
        else begin            
            ov_fifo_wdata <= 9'b0;
            o_fifo_wr <= 1'b0;
			o_desp_ack_host <= 1'b0;
        end
    end
end 
endmodule